This invention relates to testing integrated circuits, and more particularly, to screening for defects in configuration memory cells of a programmable integrated circuit.
A programmable integrated circuit typically includes thousands of configuration memory elements that store configuration data. The stored configuration data is used to configure programmable logic on the integrated circuit to perform a custom logic function, store data, or otherwise implement a user-specified design. Storing incorrect configuration data due to defects in the configuration memory cells can cause unexpected errors when performing a user-specified function.
Conventional methods of screening for configuration-related defects in a programmable integrated circuit involve writing test configuration data to each configuration random access memory (CRAM) element, unloading the stored CRAM content, and then comparing it to the test data to identify errors. Typically, the integrated circuit chip is held in a dedicated test mode while CRAM content is read out serially from each row of configuration memory to off-chip error detection circuitry.
In practice, this conventional testing method requires the programmable integrated circuit to include a large number of input-output (I/O) pins for testing purposes. Since the contents of multiple rows of CRAM memory are typically unloaded serially through a single I/O pin, high testing speeds cannot be achieved without including a substantial amount of dedicated unloading hardware. Moreover, conventional testing methods are typically performed in the factory prior to shipping and cannot be performed in-field during early stages of the device lifecycle.
It is within this context that the embodiments described herein arise.